1. Field of the Invention
The present invention relates to a memory controller. More particularly, this invention relates to the calibration of a memory controller which is configured to transmit a data signal, a data strobe signal and a mask signal to a memory.
2. Background
It is known to provide a memory controller configured to transmit a data signal, a data strobe signal and a mask signal to a memory, wherein each transition of the data strobe signal indicates a sample point for the data signal and the mask signal indicates a validity of the data signal. A typical contemporary example of such a memory controller is as part of a dual data rate (DDR) dynamic-random access memory (DRAM) system, in which write data (DQ) transmitted from the memory controller to the DRAM modules and a write data mask (DM) are captured on both the rising and the falling edge of the data strobe signal (DQS). The memory controller makes use of the mask signal (DM) to indicate at any given sample point for the data signal whether that data signal should be interpreted as valid data or not.
According to the state of the art, the corresponding JEDEC specification standard (JESD79-3E) requires the write data eye to present at the centre of DQS to balance the requirements of set-up/hold times and noise tolerance. However, as differential data rates increase, for example at the DDR data rates above 1600 Mb/s DDR3 system, the write data eye training process becomes particularly difficult, because of the presence of system jitter, PCB trace skew and DRAM uncertainty which render known automated self calibration systems unreliable. In high frequency regimes (for example operating at data rates of 2133 Mb/s, where the ideal data eye has an opening of only 468 ps), typical system jitter, PCB trace skew and DRAM uncertainty are such that the above mentioned technique of simply seeking the set DQS in the centre of the DQ bus is not reliable.
Background information related to known DDR write data eye training procedures can be found in: the publication “Algorithm for Adjustment of DDR Write Interface Timing”, Patrick Fleming/Pawel Ostropolski (Intel), ISSC, 2008 available at http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=4780944, as well as in the following patent publications:
1. “Software-Controlled Dynamic DDR Calibration”, Andrew Hadley et al, US20080276133;
2. “Scheme for optimal settings for DDR interface”, Darren Neuman et al, U.S. Pat. No. 7,111,111;
3. “Two dimensional data eye centering for source synchronous data transfers”, John F. Zumkehr et al, U.S. Pat. No. 7,036,053;
4. “Fast data eye retraining for a memory”, Andre Schaefer, U.S. Pat. No. 8,037,375;
5. “Memory link training”, Bryan L. Spry et al, U.S. Pat. No. 7,886,174; and
6. “DDR II write data capture calibration”, Wen Li et al, U.S. Pat. No. 7,165,185.
It would be desirable to provide an improved technique for calibrating a memory controller for data transmission for operation at high data rates to achieve an improved write eye opening in the presence of typical system jitter, PCB trace skew and DRAM uncertainty.